1. Field of the Invention
The present invention relates to a semiconductor memory device having a plurality of memory cells each storing data and a sense amplifier amplifying data of a selected memory cell, and particularly relates to a semiconductor memory device employing a single-ended sense amplifier amplifying data read out from each bit line, and relates to a control method thereof.
2. Description of Related Art
As capacity of semiconductor memory devices such as a DRAM have recently become large, a large number of memory cells connected to each bit line in a memory cell array have been required, and there arise a performance problem due to an increase in parasitic capacitance and parasitic resistance. As measures against such a problem, a semiconductor device having a memory cell array in which a hierarchical structure is formed with local bit line lines and global bit lines has been proposed. If such a hierarchical memory cell array is employed, the length of the local bit lines can be shorter than that of the global bit lines, and the number of memory cells connected thereto can be suppressed so that a configuration advantageous for reducing the parasitic capacitance and resistance can be achieved. Further, since the number of memory cells connected to the local bit line is reduced, a single-ended sense amplifier can be employed without using a differential sense amplifier, thereby suppressing an increase in circuit scale.
Generally, a standby mode of a DRAM is shifted to a self refresh mode in which access from outside is blocked off to retain data stored in memory cells. It is desirable that a time interval for performing refreshing in the self refresh mode is set longer than that for performing refreshing in a normal operation so as to suppress consumption current. Information is stored as an electric charge on a capacitor of each memory cell of the DRAM, and the accumulated charge on the capacitor dissipates due to leak current. The dissipation of the electric charge due to the leak current causes a signal voltage to be reduced, particularly when the memory cell stores high level data, and thereby a decrease of sensing margin of the sense amplifier occurs. Methods for increasing the sensing margin for memory cells storing high level data in the self refresh mode have been conventionally proposed (Refer to, for example, Patent References 1 and 2).    Patent Reference 1: Japanese Patent Application Laid-open No. H2-29989    Patent Reference 2: Japanese Patent Application Laid-open No. H10-55667
However, according to the method disclosed in the Patent Reference 1, a reference voltage of a sense amplifier in the self refresh mode is set lower than that in the normal operation so as to increase the sensing margin. However, there is a problem that this method cannot be applied to a case of using the single-ended sense amplifier to which the reference voltage is not applied. Further, according to the method disclosed in the Patent Reference 2, high level data of the memory cell in the self refresh mode is higher than that in the normal operation so as to increase the sensing margin. However this method has a problem of a decrease in reliability of the capacitor due to high electric field applied to the capacitor of the memory cell.
In this manner, according to the conventional technique, it is difficult to achieve a configuration capable of obtaining the sensing margin without changing the form of memory cells or the like in a large-capacity semiconductor memory device employing the hierarchical structure of bit lines and the single-ended sense amplifier for the purpose of reducing the consumption current.